1 features 4 digitally controlled amplifiers 15 gain/attenuation steps 3 amplifiers, with a 3db range in 0.43db steps 1 'volume' amplifier, with a 14db range in 2db steps fx019 brief description this product replaces the need for manual trimming of audible signals by using the host microprocessor to digitally control the set-up of all audio levels during development, production/calibration and operation. applications include: (i) control, adjustment and set-up of communications equipment by an intelligent ate without manual intervention C eg. deviation, microphone and l/s levels, rx audio level etc. (ii) automatic dynamic compensation of drift caused by variations in temperature, linearity, etc. (iii)fully automated servicing and re-alignment. the fx019 is a low-power, single 5-volt cmos device available in plastic dil and small outline (s.o.i.c.) smd package versions. publication d/019/4 december 1995 8-bit serial data control output mute function audio and data gain control applications telecoms, radio and industrial applications cml semiconductor products fx019 2 3 3 3 4 4 serial data input load/latch load/latch chip select 1 1 2 2 ch1 ch2 ch4 ch3 v dd v bias serial clock input v ss 8-bit serial data input and line decoders controlled audio output lines volume digitally controlled quad amplifier array product information the fx019 digitally adjustable amplifier array is available to replace trimmer potentiometers and volume controls in cellular, pmr, telephony and communications applications where d.c., voice or data signals need adjustment. the fx019 is a single-chip lsi consisting of four digitally controlled amplifier stages, each with 15 distinct gain/attenuation steps. control of each individual amplifier is by an 8-bit serial data stream. three of the amplifier stages offer a +/-3db range in steps of 0.43db, whilst the remaining amplifier offers a +/-14db range in steps of 2db, and is suggested for volume control applications. each amplifier includes a 16th 'off' state which when applied, mutes the output audio from that channel. this array uses a chip select input to select one of two fx019s in a system. fig.1 functional block diagram
2 pin number function FX019DW fx019p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 analogue inputs : these individual amplifier inputs are self-biasing, a.c. input analogue signals must be capacitively coupled to these pins, as shown in figure 2. note that amplifiers ch1 to ch4 are 'inverting amplifiers.' controlled analogue outputs : the individual "gain controlled" amplifier outputs. ch1 to ch3 range from -3db to +3db in 0.43db steps, ch4 could be utilized as a volume control, ranging from -14db to +14db in 2.0db steps. in the off mode there is no output from the selected amplifier. serial clock : this external clock pulse input is used to clock in the control data. see figure 4, serial control data load timing. this input has an internal 1m w pullup resistor. load/latch : governs the loading and execution of the control data. during serial data loading this input should be kept at a logical '0' to ensure that data rippling past the latches has no effect. when all 8 bits have been loaded, this input should be strobed '0' - '1' - '0' to latch the new data in. data is executed on the falling edge of the strobe. if the load/latch input is used this pin should be left open circuit. this input has an internal 1m w pullup resistor. load/latch : the inverted load/latch input. this function governs the loading and execution of the control data. during serial data loading this input should be kept at a logical '1' to ensure that data rippling past the latches has no effect. when all 8 bits have been loaded, this input should be strobed '1' - '0' - '1' to latch the new data in. data is executed on the rising edge of the strobe. if the load/latch input is used this pin should be left open circuit. this input has an internal 1m w pulldown resistor. ch1 input : ch2 input : ch3 input : ch4 input : v ss : negative supply rail (gnd). v bias : the output of the on-chip bias circuitry, held at v dd /2. this pin should be decoupled to v ss as shown in figure 2. ch4 output : ch3 output : ch2 output : ch1 output : chip select : a logic input to select one of two fx019 microcircuits in a system, see table 1. this input has an internal 1m w pulldown resistor. control data input : operation of the 4 amplifier channels (ch1 C ch4) is controlled by the 8 bits of data entered serially at this pin. the data is entered (bit 7 to bit 0) on the rising edge of the external serial clock. the data format is described in tables 1, 2 and figure 4. this input has an internal 1m w pullup resistor. v dd : positive supply rail. a single +5-volt power supply is required.
3 fig.3 sinad vs input level C typical values application notes input level db sinad (db) 30 40 50 60 -40 -30 -20 -10 0 10.0 25.0 75.0 250.0 775.0 1000.0 1730.0 -17 110.0 mvrms 7.0 input frequency = 1.0khz input level 0db ref = 775mvrms ch1 2, 3 or 4 gain set to 0db v dd v dd v ss c 6 c 1 c 2 c 3 c 4 c 5 v ss v bias v ss 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 fx019 serial clock input control data input chip select channel 1 output channel 2 output channel 3 output channel 4 output channel 1 input channel 2 input channel 3 input channel 4 input load/latch load/latch application recommendations (f) analogue tracks should not run parallel to digital tracks. (g) a "ground plane" connected to v ss will assist in eliminating external pick-up on the channel input and output pins. (h) do not run high-level output tracks close to low- level input tracks. (i) input signal amplitudes should be applied with due regard to figure 3. (a) a noisy or badly regulated power supply can cause instability and/or variance of selected gains. (b) care should be taken on the design and layout of the printed circuit board. (c) all external components (figure 2) should be kept close to the fx019 package. (d) inputs and outputs should be screened wherever possible. (e) tracks should be kept short. to avoid excess noise and instability in the final installation it is recommended that the following points be noted. notes (1) channel amplifiers 1 to 4 are inverting amplifiers. (2) analogue input capacitors c 1 to c 4 are only required for a.c. input signals, d.c. input signals do not require these components. component value c 1 to c 4 0.1f c 5 1.0f c 6 1.0f tolerances: c = 20% fig.2 external component connections
4 table 2 gain control word format bit 3 bit2 bit 1 bit 0 stage 1, 2, 3 stage 4 msb lsb (0.43db) (2.0db) 0000 off off 0001 -3.0 -14.0db 0010 -2.571 -12.0 0011 -2.143 -10.0 0100 -1.714 -8.0 0101 -1.286 -6.0 0110 -0.857 -4.0 0111 -0.428 -2.0 1000 0 0 1001 0.428 2.0 1010 0.857 4.0 1011 1.286 6.0 1100 1.714 8.0 1101 2.143 10.0 1110 2.571 12.0 1111 3.0 14.0 t llw load/latch pulse width t llo load/latch over time t ds data set-up time t dh data hold time t lld load/latch delay timing t pwh serial clock "high" pulse width t pwl serial clock "low" pulse width the gain of each amplifier block (channel 1 to channel 4) in the fx019 is set by a separate 8-bit data word ( bit 7 to bit 0 ). this 8-bit word, consisting of 4 address bits (bit 7 to bit 4) and 4 gain control bits (bit 3 to bit 0), is loaded to the control data input in serial format using the external data clock. data loading the 8-bit data word is loaded bit 7 first and bit 0 last. bit 7 must be a logic 1 to address the chip. if bit 7 in the word is a logic 0 that 8-bit word will not be executed. the chip select input permits the use of two devices in a system; to facilitate this, bit 6 can be either a logic 0 or 1. figure 4 (below) shows the timing information required to load and operate this device. control data and timing fig.4 serial control data loading diagram chip 1 chip 2 table 1 address word format bit 7 bit 6 bit 5 bit 4 channel chip chip msb lsb selected select number 1000 1 0 1001 2 0 1010 3 0 1011 4 0 1100 1 1 1101 2 1 1110 3 1 1111 4 1 data is loaded to the fx019 on the rising edge of the serial clock. loaded data is executed on the falling (rising) edge of the load/latch (load/latch) pulse. table 1 shows the format of each 4-bit address word, table 2 shows the format of each gain control word with figure 4 describing the data loading operation and timing. serial data clock t pwl t pwh t ds loaded last logic '1' loaded first bit 7 bit 6 bit 1 bit 0 t dh serial data in (one 8-bit word) t llo 8th clock pulse next clock pulse t lld t llw load/latch load/latch
5 specification absolute maximum ratings exceeding the maximum rating can result in device damage. operation of the device outside the operating limits is not implied. supply voltage -0.3 to 7.0v input voltage at any pin (ref v ss = 0v) -0.3 to (v dd + 0.3v) sink/source current (supply pins) +/- 30ma (other pins) +/- 20ma total device dissipation @ t amb 25c 800mw max. derating 10mw/c operating temperature range: FX019DW/p -40c to +85c (plastic) storage temperature range: FX019DW/p -40c to +85c (plastic) operating limits all device characteristics are measured under the following conditions unless otherwise specified: v dd = 5.0v, t amb = 25c. audio level 0db ref: = 775mvrms. amplifier gain set = 0db. characteristics see note min. typ. max. unit static values supply voltage (v dd ) 4.5 5.0 5.5 v supply current - 1.5 - ma dynamic values control functions input logic '1' 3.5 C C v input logic '0' C C 1.5 v digital input impedances 0.5 1.0 C m w amplifier stages (general) bandwidth (-3db) 20.0 C C khz output impedance C 1.0 - k w total harmonic distortion 1 C 0.35 0.5 % output noise level (per stage) 2 C 180.0 400.0 vrms onset of clipping 3 C 1.73 C vrms gain variation 4 C C 0.1 db interstage isolation C 60.0 C db trimmer stages (ch1 C ch3) gain -3.0 +3.0 db gain per step (15 in no.) C 0.43 C db step error 5 C C 0.2 db input impedance 100.0 C C k w volume stage (ch4) gain -14.0 +14.0 db gain per step (15 in no.) C 2.0 C db step error 5 C C 0.4 db input impedance 50.0 C C k w timing (figure 4) serial clock "high" pulse width (t pwh ) 250 C C ns serial clock "low" pulse width (t pwl ) 250 C C ns data set-up time (t ds ) 150 C C ns data hold time (t dh ) 50.0 C C ns load/latch pulse width (t llw ) 150 C C ns load/latch delay (t lld ) 200 C C ns load/latch over (t llo ) C C 50.0 ns serial data clock frequency C C 2.0 mhz notes 1. gain set 0db, input level 1khz -3.0db (549mvrms). 2. with an a.c short-circuit input, measured in a 30khz bandwidth. 3. see figure 3. 4. over the temperature and supply voltage range. 5. with reference to a 1.0khz signal.
6 handling precautions the fx019 is a cmos lsi circuit which includes input protection. however precautions should be taken to prevent static discharges which may cause damage. cml does not assume any responsibility for the use of any circuitry described. no circuit patent licences are implied and cml reserves the right at any time without notice to change the said circuitry. ordering information FX019DW 16-pin plastic s.o.i.c. (d4) fx019p 16-pin plastic dil (p3) package outlines the fx019 is available in the package styles outlined below. mechanical package diagrams and specifications are detailed in section 10 of this document. pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. not to scale max. body length 19.24mm max. body width 6.41mm stand-off 0.51mm not to scale max. body length 10.31mm max. body width 7.59mm stand-off 0.20mm FX019DW 16-pin plastic s.o.i.c. (d4) fx019p 16-pin plastic dil (p3)
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